报告人
说明
CEPC plans to utilize a large-area, fine-pitch, low-material, fast-readout and economic silicon-based tracker system to achieve exceptional spatial resolution. CMOS technology presents an appealing solution due to its high performance and cost-effectiveness. Compared to hybrid silicon pixel sensors, the CMOS process allows for a smaller size while guaranteeing a lower amount of material budget. It is also a potential candidate for future upgrades to other experiments, i.e., the LHCb Upstream Tracker. Unlike many CMOS processes that require modifications and enhancements to generate sufficient signal, the commercially available high resistance wafer based High Voltage CMOS (HVCMOS) is intrinsically radiation hard and has large capacitance for signal acquisition. The potentially lifting noise and power consumption of HVCMOS, compared to the small-electrode CMOS, are tolerable for large area tracker. Moreover, the HVCMOS production process has further developed in domestic foundry recently, could be customized commercially.
