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摘要： 为了满足环形正负电子对撞机（CEPC）顶点探测器对极高空间和时间分辨率的要求，CPV-4芯片采用了先进的3D-SOI像素工艺。该工艺通过将数字芯片与模拟芯片垂直堆叠成3D结构，显著减小了像素尺寸和功耗，从而有效提升了空间分辨率。芯片的下层集成了传感器和模拟前端，而上层则负责处理击中信息的存储和读出，同时采用事例驱动的AERD结构以提升时间分辨率。鉴于3D-SOI工艺制作的复杂性，我们开发了一套基于IPbus协议的灵活且可靠的数据获取系统，确保精确验证芯片的功能和性能。该系统不仅支持3D-SOI芯片设计和制造过程的验证，也适用于其他复杂像素芯片的测试与评估。利用测试系统，我们对单独的上层逻辑芯片及整体CPV-4 3D芯片进行了全方位的功能测试，验证了3D工艺的可行性。同时，测试结果为CPV-4以及3D工艺中潜在的问题提供了诊断分析和改进的依据。
Abstract: To meet the requirements of the Circular Electron Positron Collider (CEPC) vertex detector for ultra-high spatial and temporal resolution, the CPV-4 chip adopts advanced 3D-SOI pixel technology. This technology significantly reduces pixel size and power consumption by vertically stacking the digital and analog chips into a 3D structure, thus effectively enhancing spatial resolution. The bottom layer of the chip integrates the sensor and analog front-end, while the top layer is responsible for the storage and readout of hit information, employing an event-driven AERD structure to improve temporal resolution. Given the complexity of the 3D-SOI process, we have developed a flexible and reliable data acquisition system based on the IPbus protocol to ensure accurate performance verification of the chip. The system supports not only the validation of the SOI-3D chip design and manufacturing process but is also suitable for testing and evaluating other complex pixel chips. Utilizing the test system, we have conducted extensive functional testing on the separate top-layer logic chip and the complete CPV-4 3D chip, validating the feasibility of the 3D process. The test results provide diagnostic analysis and a basis for improvement for potential issues within the CPV-4 and the 3D process.
